TPU SoC Integration Engineer, Cloud

MINIMUM QUALIFICATIONS:

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer

Science, or a related field, or equivalent practical experience.

* 8 years of experience in ASIC design or RTL design.

* Experience with SoC design and integration.

* Experience with multi-chiplet SoC integration.

* Experience with SoC Design for Testing (DFT) planning.

* Experience scripting in Python or Perl or Tcl.

PREFERRED QUALIFICATIONS:

* Master's degree or PhD in Electrical Engineering, Computer Engineering or

Computer Science, with an emphasis on computer architecture.

* Experience with SoC signoff–Logic Equivalence Check (LEC)/Lint/Unified Power

Format (UPF)/CDC/Reset Domain Crossing (RDC) flows.

* Cross-functional experience with Design Verification (DV), Physical Design

(PD), Clock Domain Crossing (CDC) and DFT teams.

* Experience designing and constructing ASIC Input/Output (IO) pad-rings.

* Knowledgeable in 3DIO methodology, voltage and clock domain partitioning.

* Knowledgeable in ASIC top-level Static Timing Analysis (STA) and clock

planning.

ABOUT THE JOB:

In this role, you’ll work to shape the future of AI/ML hardware acceleration.

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit)

technology that powers Google's most demanding AI/ML applications. You’ll be

part of a team that pushes boundaries, developing custom silicon solutions that

power the future of Google's TPU. You'll contribute to the innovation behind

products loved by millions worldwide, and leverage your design and verification

expertise to verify complex digital designs, with a specific focus on TPU

architecture and its integration within AI/ML-driven systems.

As an ASIC SoC Integration Engineer, you will drive the construction and

architectural execution of advanced multi-chiplet SoC integration projects. This

role demands deep cross-domain collaboration, working closely with ASIC

Packaging and Interposer teams to orchestrate complex interposer planning and

implementation, alongside multi-die DFT connectivity and packaging routing. You

will leverage your understanding of multi-die integration concerns, 3DIO

technologies, and voltage and clock domain partitioning to build robust systems

while addressing critical physical design implementation concerns. Utilizing

your experience in architecting RTL solutions with software-based construction,

instantiation, and generation, you will manage SoC IP integration and

participate in layout design decisions and SoC-level sign-off activities,

shaping the future of high-performance silicon layout. You will own the upper

levels of RTL hierarchy up-to the package level and work closely with the

Verification and Emulation teams to debug connectivity issues and optimize RTL

compilation. You will manage RTL deliverables to all stakeholders and plan RTL

integration activities to meet project schedules.

The AI and Infrastructure team is redefining what’s possible. We empower Google

customers with breakthrough capabilities and insights by delivering AI and

Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our

customers include Googlers, Google Cloud customers, and billions of Google users

worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering

the development of our cutting-edge AI models, delivering unparalleled computing

power to global services, and providing the essential platforms that enable

developers to build the future. From software to hardware our teams are shaping

the future of world-leading hyperscale computing, with key teams working on the

development of our TPUs, Vertex AI for Google Cloud, Google Global Networking,

Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills,

experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google

[https://www.google.com/about/careers/applications/benefits/].

RESPONSIBILITIES:

* Lead advanced SoC integration projects from concept to final delivery,

managing project milestones, deliverables, and cross-functional schedules.

* Partner with ASIC teams on complex interposer and package design, and resolve

multi-die physical design tests leveraging 3DIO and domain partitioning

expertise.

* Utilize software-based construction to seamlessly integrate SoC IPs and

maintain complete ownership of the upper-level RTL hierarchy up to the

package level.

* Collaborate closely with Verification and Emulation teams to resolve complex

connectivity issues and optimize system compilation.

* Participate in critical layout design decisions and SoC-level sign-off

activities to ensure robust, high-performance silicon delivery.