TPU Hardware Design Engineer, Cloud

MINIMUM QUALIFICATIONS:

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer

Science, a related field, or equivalent practical experience.

* 4 years of experience in RTL design.

* Experience with digital design and microarchitecture design.

* Experience in design optimizing for performance, power, and area.

PREFERRED QUALIFICATIONS:

* Master's degree or PhD in Electrical Engineering, Computer Engineering or

Computer Science, with an emphasis on computer architecture.

* 5 years of experience in RTL design.

* Experience with scripting languages (i.e., Python or Perl).

* Experience with Linting, Clock Domain Crossing (CDC), Reset Domain Crossing

(RDC), Logic Equivalence Check (LEC).

* Experience architecting RTL solutions and with ASIC synthesis flows.

* Cross-functional engagement with Design Verification (DV) and Physical Design

(PD) teams.

ABOUT THE JOB:

In this role, you’ll work to shape the future of AI/ML hardware acceleration.

You will have an opportunity to drive TPU (Tensor Processing Unit) technology

that powers Google's most demanding AI/ML applications. You’ll be part of a team

that pushes boundaries, developing custom silicon solutions that power the

future of Google's TPU. You'll contribute to the innovation behind products

loved by millions worldwide, and leverage your design and verification expertise

to verify complex digital designs, with a specific focus on TPU architecture and

its integration within AI/ML-driven systems.

As an RTL Design Engineer on the TPU team, you will be a key contributor to the

development of Google's AI accelerators. You will leverage your expertise in

digital logic design, computer architecture, and RTL coding to create innovative

and efficient hardware solutions. You will address challenging technical

problems at the forefront of AI hardware, working in a dynamic and collaborative

environment. You will join the team designing and developing the on-chip network

of Google's next-generation Tensor Processing Units (TPUs), the custom-built

accelerators powering our AI and machine learning workloads in data centers. You

will be responsible for the microarchitecture, design, implementation, and

integration of key digital logic blocks within the TPU. This role requires close

collaboration with cross-functional teams, including Verification, Physical

Design, Validation, and Firmware, to deliver hardware. You will own critical

design deliverables, help with integration efforts, and contribute to the

continuous improvement of our design methodologies and flows.

The AI and Infrastructure team is redefining what’s possible. We empower Google

customers with breakthrough capabilities and insights by delivering AI and

Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our

customers include Googlers, Google Cloud customers, and billions of Google users

worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering

the development of our AI models, delivering unparalleled computing power to

global services, and providing the essential platforms that enable developers to

build the future. From software to hardware our teams are shaping the future of

world-leading hyperscale computing, with key teams working on the development of

our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center

operations, systems research, and much more.

Individual pay is determined by factors including job-related skills,

experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google

[https://www.google.com/about/careers/applications/benefits/].

RESPONSIBILITIES:

* Define TPU microarchitecture and develop high-quality, performant, and

power-efficient SystemVerilog RTL code for complex digital designs.

* Partner with Verification teams to develop test plans, debug RTL, and ensure

functional correctness, alongside supporting post-silicon validation efforts.

* Collaborate closely with the Physical Design team to successfully meet

stringent timing, area, power, and manufacturability requirements.

* Work seamlessly with internal Partner teams to support and drive critical

design integration efforts across the ecosystem.