About the role

What will you do at Google?

MINIMUM QUALIFICATIONS:

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer

Science, or a related field, or equivalent practical experience.

* 4 years of experience with silicon or semiconductors (e.g., digital design,

silicon validation, computer architecture, product engineering).

* Experience scripting in one or more programming languages (e.g., Python).

PREFERRED QUALIFICATIONS:

* Master's degree or PhD in Electrical Engineering, Computer Engineering or

Computer Science, with an emphasis on computer architecture.

* Experience in product engineering: managing and optimizing test content,

debugging issues, performing RMA/FA, and conducting root cause analysis.

* Experience collaborating with silicon vendors, contract manufacturers, and

supply chain partners to improve test quality, reliability, and yield.

* Experience with large digital SoCs, focusing on functional domain

engineering, alongside utilizing complex software stacks to perform

functional testing, investigations, and log/data analysis.

* Experience with high-speed interfaces, ASIC interfaces, memory systems (HBM),

power system features, or high-power ASICs.

ABOUT THE JOB:

In this role, you’ll work to shape the future of AI/ML hardware acceleration.

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit)

technology that powers Google's most demanding AI/ML applications. You’ll be

part of a team that pushes boundaries, developing custom silicon solutions that

power the future of Google's TPU. You'll contribute to the innovation behind

products loved by millions worldwide, and leverage your design and verification

expertise to verify complex digital designs, with a specific focus on TPU

architecture and its integration within AI/ML-driven systems.

In this role, you will

support integration and testing on hardware emulation
platforms. During post-silicon, you will lead validation, bringup, and system
qualification across power features, interfaces, HBM memory, compute
functionality, and overall performance. Finally, you will provide ongoing
engineering support during chip manufacturing, deployment, and field
operations—monitoring quality and reliability while optimizing test efficiency,
RMA/FA root-cause analysis, and process workflows.
The AI and Infrastructure team is redefining what’s possible. We empower Google
customers with breakthrough capabilities and insights by delivering AI and
Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our
customers include Googlers, Google Cloud customers, and billions of Google users
worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering
the development of our cutting-edge AI models, delivering unparalleled computing
power to global services, and providing the essential platforms that enable
developers to build the future. From software to hardware our teams are shaping
the future of world-leading hyperscale computing, with key teams working on the
development of our TPUs, Vertex AI for Google Cloud, Google Global Networking,
Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills,
experience, and relevant education or training.
US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google
[https://www.google.com/about/careers/applications/benefits/].
RESPONSIBILITIES:
* Own sustaining phases of the silicon development lifecycle. Monitor, debug,
and deploy corrective actions for quality and reliability issues in
manufacturing, deployment, and serving.
* Optimize test performance across manufacturing and deployment. Partner with
cross-functional teams to improve test coverage and reduce overall test time.
* Drive triage, debugging, and corrective actions across all deployment stages.
Support rapid resolution in early NPI to reduce test failures and escapes,
driving process improvements as necessary.
* Collaborate with supply chain, contract manufacturing, and vendors to
implement firmware, software, hardware, or process improvements.
* Investigate, reproduce, and root-cause field failures to drive resolution,
focusing primarily on functional operations alongside DFT/DFD structural
testing.

Which skills does this role require?

Silicon validationDigital designPythonSoCPower systemsHardware emulationFirmwareSilicon ValidationSemiconductorsDigital DesignHardware EmulationDFTDFDManufacturingNPIHyperscale ComputingVertex AIData Center OperationsSystem QualificationGCPMachine Learning

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