Senior Design and Integration Engineer, Cloud TPU

MINIMUM QUALIFICATIONS:

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer

Science, a related field, or equivalent practical experience.

* 8 years of experience in RTL design.

* Experience with digital design and microarchitecture design.

* Experience in optimizing for performance, power, and area.

* Cross-functional experience with Design Verification (DV) and Physical Design

(PD) teams.

PREFERRED QUALIFICATIONS:

* Master's degree or PhD in Electrical Engineering, Computer Engineering or

Computer Science, with an emphasis on computer architecture.

* 10 years of RTL design experience.

* 4 years of experience in power optimization and experience with power

analysis tools like PowerArtist and PTPX.

* Experience with Linting, CDC, RDC, LEC and experience with Scripting

languages (i.e. Python or Perl).

* Experience optimizing RTL solutions, RTL design methodologies and automate

front-end engineering flows.

* Experience in design automation, architecting RTL solutions and ASIC

Synthesis flows.

ABOUT THE JOB:

In this role, you’ll work to shape the future of AI/ML hardware acceleration.

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit)

technology that powers Google's most demanding AI/ML applications. You’ll be

part of a team that pushes boundaries, developing custom silicon solutions that

power the future of Google's TPU. You'll contribute to the innovation behind

products loved by millions worldwide, and leverage your design and verification

expertise to verify complex digital designs, with a specific focus on TPU

architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the On-Chip Network of Google's

next-generation Tensor Processing Units (TPUs), the custom-built accelerators

powering our AI and machine learning workloads in datacenters. You will be

responsible for the microarchitecture, design, implementation, and integration

of key digital logic blocks within the TPU. Your role requires close

collaboration with cross-functional teams, including Verification, Physical

Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own

critical design deliverables, help with integration efforts, and contribute to

the continuous improvement of our design methodologies and flows.

As an RTL Design Engineer on the TPU team, you will be a key contributor to the

development of Google's AI accelerators. You will leverage your expertise in

digital logic design, computer architecture, and RTL coding to create innovative

and efficient hardware solutions.The AI and Infrastructure team is redefining

what’s possible. We empower Google customers with breakthrough capabilities and

insights by delivering AI and Infrastructure at unparalleled scale, efficiency,

reliability and velocity. Our customers include Googlers, Google Cloud

customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of

AI models, delivering unparalleled computing power to global services, and

providing the essential platforms that enable developers to build the future.

From software to hardware our teams are shaping the future of world-leading

hyperscale computing, with key teams working on the development of our TPUs,

Vertex AI for Google Cloud, Google Global Networking, Data Center operations,

systems research, and much more.Individual pay is determined by factors

including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google

[https://www.google.com/about/careers/applications/benefits/].

RESPONSIBILITIES:

* Define and document the microarchitecture for digital designs within the TPU.

* Partner with Verification to develop test plans and debug RTL, and

collaborate with Physical Design to achieve timing, area, power, and

manufacturability goals.

* Drive critical power optimization and automation initiatives across all

on-chip-network components and subsystems.

* Support post-silicon validation and hardware debugging efforts to ensure

successful deployment.

* Lead the development and enhancement of internal design tools, flows, and

engineering methodologies.