Senior ASIC Cloud Design Verification Engineer

MINIMUM QUALIFICATIONS:

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer

Science, a related field, or equivalent practical experience.

* 8 years of experience with design verification.

* Experience in verifying digital logic at RTL using SystemVerilog/UVM for

ASICs.

PREFERRED QUALIFICATIONS:

* Master's degree or PhD in Electrical Engineering, Computer Engineering or

Computer Science, with an emphasis on computer architecture.

* 10 years of experience with industry standard tools, languages and

methodologies relevant to the development of silicon-based ICs and chips.

* Experience with the full verification life cycle.

* Experience with three or more SoC projects/cycles and verifying interconnect

IPs.

ABOUT THE JOB:

In this role, you’ll work to shape the future of AI/ML hardware acceleration.

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit)

technology that powers Google's most demanding AI/ML applications. You’ll be

part of a team that pushes boundaries, developing custom silicon solutions that

power the future of Google's TPU. You'll contribute to the innovation behind

products loved by millions worldwide, and leverage your design and verification

expertise to verify complex digital designs, with a specific focus on TPU

architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Engineer, you will be part of a team developing

ASICs used to accelerate computation in data centers. You will have dynamic,

multi-faceted responsibilities in areas such as project definition, design

verification and silicon bring-up. You will participate in the architecture,

documentation, and verification of the next generation of data center

accelerators.

The AI and Infrastructure team is redefining what’s possible. We empower Google

customers with breakthrough capabilities and insights by delivering AI and

Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our

customers include Googlers, Google Cloud customers, and billions of Google users

worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering

the development of our cutting-edge AI models, delivering unparalleled computing

power to global services, and providing the essential platforms that enable

developers to build the future. From software to hardware our teams are shaping

the future of world-leading hyperscale computing, with key teams working on the

development of our TPUs, Vertex AI for Google Cloud, Google Global Networking,

Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills,

experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google

[https://www.google.com/about/careers/applications/benefits/].

RESPONSIBILITIES:

* Plan the verification of complex digital design blocks by understanding the

design specification and interacting with design engineers to identify

important verification scenarios.

* Create and enhance constrained-random verification environments using

SystemVerilog and UVM.

* Identify and write all types of coverage measures for stimulus and

corner-cases.

* Debug tests with design engineers to deliver functionally correct design

blocks.

* Close coverage measures to identify verification holes and to show progress

towards tape-out.