Principal Engineer, SerDes AMS Design and Architecture

Position: Principal Engineer, SerDes AMS Design and Architecture Location: San Jose, CA Job Id: 701 # of Openings: 0 Principal Engineer, SerDes AMS Design and Architecture Location: San Jose, CA (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking a Principal Analog/Mixed Signal Design Engineer to shape the architecture of our next-generation co-packaged optics product.

You will set the AMS direction across our roadmap, help define what gets built next and why, and be the technical authority the rest of the AMS organization works with on the hardest challenges.

Key Responsibilities

• Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
• Set the AMS technical direction across our roadmap.
• Translate system-level specs into AMS subsystem architecture and block specs.
• Lead the silicon-success methodology: first-silicon-success expectations, debug discipline, characterization-to-production.
• Mentor AMS design engineers in design reviews and silicon debug.
• Drive co-design across the EIC/PIC boundary.
• Represent the AMS organization in cross-functional architecture reviews, customer technical engagements, and foundry/EDA partner discussions.
• Required

Qualifications

• B.S. in Electrical Engineering 12+ years of industry experience in analog/mixed signal design Track record of production tapeouts in advanced FinFET CMOS nodes Design experience with high speed and high precision analog blocks such as PLLs, clock distribution and multi-phase generation, TX/RX analog front ends, data converters, and references/regulators.
• Fluent with Cadence design environment and mixed-signal simulation (ADE, Layout, Spectre).
• Experience driving architectural tradeoff analysis using link budgeting tools.
• Experience designing in FinFet CMOS (7nm or below) at data rates of at least 50Gb/s and/or RF circuits operating at 25GHz or above.

Preferred Qualifications

• M.S. or Ph.D in Electrical Engineering Direct experience with optical link components, such as TIAs, high swing drivers, MRMs, and thermal control loops.
• Experience designing for chiplets, 3D stacked, or other advanced packaging applications.
• Previous experience in bringing a new AMS architectural concept from idea to production silicon.
• Demonstrated mentorship of junior designers.
• Base Salary Range: $200,000 - $260,000 NOTE TO RECRUITERS: Principals only.
• We are not accepting resumes from recruiters for this position.
• Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties.
• Please don’t send candidates to Ayar Labs, and do not contact our managers.
• Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law.
• It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship.
• Veterans are more than welcome and encouraged to apply.
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