Principal Design Verification Engineer - Formal

The candidate for this position will be expected and able to complete the following responsibilities upon hire: Own or lead Formal verification of Fabric Interconnect architectures, IPs, subsystems, and reusable Fabric components from planning through signoff. Partner with architecture, design, and verification teams to define Formal verification strategies, methodologies, test plans, and signoff criteria.

Develop and enhance Formal verification environments, assertions, abstraction models, checkers, and reusable verification collateral. Drive root-cause analysis and closure of complex design and verification issues through Formal analysis, simulation, and debug. Improve verification productivity through automation, methodologies, and AI-assisted solutions.

Coach and mentor engineers in Formal verification methodologies and best practices.

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.

As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport.

Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience. 1+ year(s) experience working on or leading projects from beginning-to-end. 5+ years of pre-silicon subsystem or IP Formal verification experience.

Demonstrated expertise applying Formal verification methodologies to complex IPs, subsystems, SoCs, or reusable library components. Demonstrated expertise in one or more of the following: Fabric Interconnects, coherency, CHI, AMBA, PCIe, CXL, protocol bridges, virtualization, security, or memory subsystems. Experience driving verification from planning through signoff across multiple product cycles.

Experience developing scalable Formal verification environments, assertions, assumptions, checkers, and reusable verification collateral. Experience solving complex cross-team technical challenges and driving verification closure. Working knowledge of simulation-based verification methodologies, including System Verilog, UVM, assertions, and coverage-driven verification.

Proficiency with Python or similar scripting languages for automation and verification productivity. Experience applying AI-assisted tools to engineering and verification workflows